157 search results - page 13 / 32 » Performance area efficiency in chip multiprocessors with mic... |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
ISVLSI
2002
IEEE
14 years 1 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
MICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
ICPPW
2008
IEEE
14 years 3 months ago
2008
IEEE
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....