157 search results - page 25 / 32 » Performance area efficiency in chip multiprocessors with mic... |
EUROPAR
2006
Springer
14 years 9 days ago
2006
Springer
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
JSAC
2008
13 years 8 months ago
2008
Multiple-input multiple-output (MIMO) detection algorithms providing soft information for a subsequent channel decoder pose significant implementation challenges due to their high ...
CODES
2009
IEEE
14 years 3 months ago
2009
IEEE
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
—In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT ...