157 search results - page 28 / 32 » Performance area efficiency in chip multiprocessors with mic... |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
APSCC
2010
IEEE
13 years 6 months ago
2010
IEEE
Middleware for web service orchestration, such as runtime engines for executing business processes, workflows, or web service compositions, can easily become performance bottleneck...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
GRID
2006
Springer
13 years 8 months ago
2006
Springer
Monitoring and correlation of streaming data from multiple sources is becoming increasingly important in many application areas. Example applications include automated commodities...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...