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2005
Tsinghua U.
14 years 6 days ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
SC
2004
ACM
14 years 4 days ago
A Performance and Scalability Analysis of the BlueGene/L Architecture
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...
SPDP
1993
IEEE
13 years 10 months ago
The Meerkat Multicomputer
Meerkat is a distributed memory multicomputer architecture that scales to hundreds of processors. Meerkat uses a two dimensional passive backplane to connect nodes composed of pro...
Robert C. Bedichek, Curtis Brown
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
13 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
BTW
2009
Springer
146views Database» more  BTW 2009»
14 years 1 months ago
Towards Flash Disk Use in Databases - Keeping Performance While Saving Energy?
Abstract: Green computing or energy saving when processing information is primarily considered a task of processor development. We, however, advocate that a holistic approach is ne...
Theo Härder, Karsten Schmidt 0002, Yi Ou, Seb...