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CASES
2005
ACM
13 years 9 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
SAINT
2003
IEEE
14 years 23 days ago
A Generalized Target-Driven Cache Replacement Policy for Mobile Environments
Caching frequently accessed data items on the client side is an effective technique to improve the system performance in wireless networks. Due to cache size limitations, cache re...
Liangzhong Yin, Guohong Cao, Ying Cai
HPCC
2009
Springer
14 years 3 days ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
LCTRTS
2009
Springer
14 years 2 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
PPOPP
1997
ACM
13 years 11 months ago
Performance Implications of Communication Mechanisms in All-Software Global Address Space Systems
Global addressing of shared data simplifies parallel programming and complements message passing models commonly found in distributed memory machines. A number of programming sys...
Beng-Hong Lim, Chi-Chao Chang, Grzegorz Czajkowski...