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3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 18 days ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
INFOCOM
1996
IEEE
13 years 11 months ago
Integrated Control of Connection Admission, Flow Rate, and Bandwidth for ATM Based Networks
: We consider the combined control problem of connection admission, flow rate, and bandwidth allocation (capacity, service-rate) under nonstationary conditions. A fluid flow model ...
Andreas Pitsillides, Petros A. Ioannou, David Tipp...
IISWC
2008
IEEE
14 years 1 months ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
ICCCN
2007
IEEE
14 years 1 months ago
A Proactive Test Based Differentiation Technique to Mitigate Low Rate DoS Attacks
— Low rate DoS attacks are emerging threats to the TCP traffic, and the VoIP traffic in the Internet. They are hard to detect as they intelligently send attack traffic inside the...
Amey Shevtekar, Nirwan Ansari
ITNG
2008
IEEE
14 years 1 months ago
Deadlock-Free Multi-Path Routing for Torus-Based NoCs
In our previous work, a Multi-Path Routing (MPR) scheme was proposed to maximize the data throughput for torus-based NoCs by utilizing multiple paths for concurrent data transmiss...
Yaoting Jiao, Mei Yang, Yingtao Jiang, Yulu Yang, ...