44 search results - page 7 / 9 » Performance evaluation of cache replacement policies for the... |
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
MICRO
2003
IEEE
14 years 23 days ago
2003
IEEE
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...
HPCA
2002
IEEE
14 years 7 months ago
2002
IEEE
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
WWW
2007
ACM
14 years 8 months ago
2007
ACM
Online auction sites have very specific workloads and user behavior characteristics. Previous studies on workload characterization conducted by the authors showed that i) bidding a...
CGO
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program perform...