54 search results - page 6 / 11 » Performance evaluation of wormhole routed network processor-... |
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
PDPTA
2003
13 years 8 months ago
2003
Routing algorithms are traditionally evaluated under Poisson-like traffic distributions. This type of traffic is smooth over large time intervals and has been shown not necessaril...
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
The switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. It is therefore crucial to study variou...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The necklace hypercube has recently been introduced as an attractive alternative to the well-known hypercube. Previous research on this network topology has mainly focused on topo...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...