NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture

In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised router components that can be used to form different routers with a varying number of ports, routing algorithms, data widths and buffer depths. A graph description representing the interconnection between these routers is used to generate a top-level VHDL description. A wormhole output-queued 2-D mesh router was created to verify the capability of NoCGEN. Various parameterized designs were synthesized to provide estimated gate counts of 129K to 695K for a number of topologies varying from a 2 x 2 mesh to a 4x4 mesh, with constant data bus size width of 32. The NoC was simulated with random traffic using a mixed SystemC / VHDL environment to ensure correctness of operation and to obtain performance and average latency. The results show an accepted load of 53% to 55.6% with an increase in buffer depth from 8 to 32...

• Type: Conference
• Year: 2004
• Where: VLSID
• Authors: Jeremy Chan, Sri Parameswaran
• Keywords: 2-D Mesh Router, Computer Architecture, Synthesizable Noc Description, Top-level Vhdl Description, VLSID 2004