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JSS
2006
104views more  JSS 2006»
13 years 7 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
IPPS
2007
IEEE
14 years 1 months ago
Message Routing and Scheduling in Optical Multistage Networks using Bayesian Inference method on AI algorithms
Optical Multistage Interconnection Networks (MINs) suffer from optical-loss during switching and crosstalk problem in the switches. The crosstalk problem is solved by routing mess...
Ajay K. Katangur, Somasheker Akkaladevi
ANCS
2011
ACM
12 years 7 months ago
A Scalability Study of Enterprise Network Architectures
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
Brent Stephens, Alan L. Cox, Scott Rixner, T. S. E...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
14 years 2 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
DAC
2006
ACM
13 years 11 months ago
Steiner network construction for timing critical nets
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li