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» Performance improvement with circuit-level speculation
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DAIS
2006
14 years 7 days ago
Using Speculative Push for Unnecessary Checkpoint Creation Avoidance
Abstract. This paper discusses a way of incorporating speculation techniques into Distributed Shared Memory (DSM) systems with checkpointing mechanism without creating unnecessary ...
Arkadiusz Danilecki, Michal Szychowiak
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
14 years 4 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
ICS
2009
Tsinghua U.
14 years 5 months ago
Combining thread level speculation helper threads and runahead execution
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...
ASPLOS
2010
ACM
14 years 5 months ago
A real system evaluation of hardware atomicity for software speculation
In this paper we evaluate the atomic region compiler abstraction by incorporating it into a commercial system. We find that atomic regions are simple and intuitive to integrate i...
Naveen Neelakantam, David R. Ditzel, Craig B. Zill...
IPPS
2000
IEEE
14 years 3 months ago
JavaSpMT: A Speculative Thread Pipelining Parallelization Model for Java Programs
This paper presents a new approach to improve performance of Java programs by extending the superthreaded speculative execution model [14, 15] to exploit coarsegrained parallelism...
Iffat H. Kazi, David J. Lilja