176 search results - page 18 / 36 » Performance improvement with circuit-level speculation |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
With the shrinking of transistors continuing to follow Moore's Law and the non-scalability of conventional outof-order processors, multi-core systems are becoming the design ...
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
IWMM
2010
Springer
14 years 5 days ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...