176 search results - page 6 / 36 » Performance improvement with circuit-level speculation |
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
JILP
2000
13 years 8 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
ISCA
1999
IEEE
14 years 21 days ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
ASYNC
1997
IEEE
14 years 19 days ago
1997
IEEE
This paper presents an in-depth case study in highperformance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rai...