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» Performance improvement with circuit-level speculation
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ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
14 years 5 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
ISCA
2006
IEEE
148views Hardware» more  ISCA 2006»
14 years 2 months ago
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
13 years 12 months ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...
IEEEPACT
1998
IEEE
14 years 20 days ago
Exploiting Method-Level Parallelism in Single-Threaded Java Programs
Method speculation of object-oriented programs attempts to exploit method-level parallelism (MLP) by executing sequential method invocations in parallel, while still maintaining c...
Michael K. Chen, Kunle Olukotun
USENIX
2003
13 years 9 months ago
Operating System I/O Speculation: How Two Invocations Are Faster Than One
We present an in-kernel disk prefetcher which uses speculative execution to determine what data an application is likely to require in the near future. By placing our design withi...
Keir Faser, Fay Chang