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» Performance of Hardware Compressed Main Memory
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ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
14 years 8 days ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
DATE
2004
IEEE
136views Hardware» more  DATE 2004»
13 years 11 months ago
Compact Binaries with Code Compression in a Software Dynamic Translator
Embedded software is becoming more flexible and adaptable, which presents new challenges for management of highly constrained system resources. Software dynamic translation is a t...
Stacey Shogan, Bruce R. Childers
COMPUTER
1998
119views more  COMPUTER 1998»
13 years 7 months ago
Virtual Memory: Issues of Implementation
ion layer3,4 hides hardware particulars from the higher levels of software but can also compromise performance and compatibility; the higher levels of software often make unwitting...
Bruce L. Jacob, Trevor N. Mudge
MICRO
2010
IEEE
154views Hardware» more  MICRO 2010»
13 years 6 months ago
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but...
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. ...
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
14 years 1 months ago
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we wi...
Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangy...