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» Performance of Hardware Compressed Main Memory
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ISW
2009
Springer
14 years 2 months ago
MAC Precomputation with Applications to Secure Memory
We present ShMAC (Shallow MAC), a fixed input length message authentication code that performs most of the computation prior to the availability of the message. Specifically, Sh...
Juan A. Garay, Vladimir Kolesnikov, Rae McLellan
ISCA
1991
IEEE
121views Hardware» more  ISCA 1991»
13 years 11 months ago
IXM2: A Parallel Associative Processor
This paper describes a parallel associative processor, IXM2, developed mainly for semantic network processing. IXM2 consists of 64 associative processors and 9 network processors,...
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, N...
INFOCOM
2012
IEEE
11 years 10 months ago
Block permutations in Boolean Space to minimize TCAM for packet classification
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
Rihua Wei, Yang Xu, H. Jonathan Chao
ISCA
2010
IEEE
284views Hardware» more  ISCA 2010»
14 years 1 months ago
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address
Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and...
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 1 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt