290 search results - page 32 / 58 » Performance of Hardware Compressed Main Memory |
PVLDB
2010
13 years 6 months ago
2010
The huge amount of temporal data generated from many important applications call for a highly efficient and scalable version index. The TSB-tree has the potential of large scalab...
IEEEPACT
2003
IEEE
14 years 1 months ago
2003
IEEE
In Thread-Level Speculation (TLS), speculative tasks generate memory state that cannot simply be combined with the rest of the system because it is unsafe. One way to deal with th...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...