290 search results - page 42 / 58 » Performance of Hardware Compressed Main Memory |
ICVS
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. This paper presents a software architecture for a softwaresynchronized multicamera setup. The software allows consistent multiimage acquisition, image processing and deci...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unl...
EH
2002
IEEE
14 years 1 months ago
2002
IEEE
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...