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» Performance of Hardware Compressed Main Memory
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ICCAD
1999
IEEE
92views Hardware» more  ICCAD 1999»
14 years 14 days ago
Interface and cache power exploration for core-based embedded system design
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
Tony Givargis, Jörg Henkel, Frank Vahid
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
13 years 6 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
14 years 2 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
IEEEPACT
2008
IEEE
14 years 2 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
LCTRTS
2000
Springer
13 years 11 months ago
An Integrated Push/Pull Buffer Management Method in Multimedia Communication Environments
Multimedia communication systems require not only high-performance computer hardware and highspeed networks, but also a buffer management mechanism to process voluminous data effi...
Sungyoung Lee, Hyonwoo Seung, Taewoong Jeon