69 search results - page 12 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
SIGARCH
2008
13 years 8 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
SPAA
1996
ACM
14 years 21 days ago
1996
ACM
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
ANCS
2008
ACM
13 years 10 months ago
2008
ACM
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
CN
2008
13 years 8 months ago
2008
Electrical-to-optical domain conversions and vice versa (denoted by O/E/O conversions) for each hop in optical core transport networks impose considerable capital and financial ov...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...