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FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 12 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
VISUALIZATION
1998
IEEE
13 years 11 months ago
Efficient warping for architectural walkthroughs using layered depth images
This paper presents efficient image-based rendering techniques used in the context of an architectural walkthrough system. Portals (doors and windows) are rendered by warping laye...
Voicu Popescu, Anselmo Lastra, Daniel G. Aliaga, M...
ISPA
2007
Springer
14 years 1 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
SBACPAD
2003
IEEE
103views Hardware» more  SBACPAD 2003»
14 years 18 days ago
Performance Analysis Issues for Parallel Implementations of Propagation Algorithm
This paper presents a theoretical study to evaluate the performance of a family of parallel implementations of the propagation algorithm. The propagation algorithm is used to an i...
Leonardo Brenner, Luiz Gustavo Fernandes, Paulo Fe...
ICPR
2004
IEEE
14 years 8 months ago
Face Verification System Architecture Using Smart Cards
A smart card based face verification system is proposed in which the feature extraction and decision making is performed on the card. Such an architecture has many privacy and sec...
Josef Kittler, Kieron Messer, Thirimachos Bourlai