955 search results - page 26 / 191 » Performance optimization of multiple memory architectures fo... |
PARA
2004
Springer
14 years 2 months ago
2004
Springer
During the last half-decade, a number of research efforts have centered around developing software for generating automatically tuned matrix multiplication kernels. These include ...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
Consider any known sequential algorithm for matrix multiplication over an arbitrary ring with time complexity O N , where 2 3. We show that such an algorithm can be parallelize...
MEMOCODE
2010
IEEE
13 years 7 months ago
2010
IEEE
A new language, Feldspar, is presented, enabling high-level and platform-independent description of digital signal processing (DSP) algorithms. Feldspar is a pure functional langua...
DATE
2002
IEEE
14 years 2 months ago
2002
IEEE
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...