955 search results - page 28 / 191 » Performance optimization of multiple memory architectures fo... |
CODES
2011
IEEE
12 years 8 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
CONNECTION
2007
13 years 8 months ago
2007
In physical implementations of associative memory, wiring costs play a significant role in shaping patterns of connectivity. In this study of sparsely-connected associative memory...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
HIPC
2000
Springer
14 years 18 days ago
2000
Springer
Many scientific applications manipulate large amount of data and, therefore, are parallelized on high-performance computing systems to take advantage of their computational power a...
SOFTVIS
2003
ACM
14 years 2 months ago
2003
ACM
Optimizing the performance of shared-memory NUMA programs remains something of a black art, requiring that application writers possess deep understanding of their programs’ beha...