955 search results - page 34 / 191 » Performance optimization of multiple memory architectures fo... |
111
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FPL
2009
Springer
15 years 7 months ago
2009
Springer
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
152
Voted
ICPPW
2007
IEEE
15 years 9 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
123
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VLDB
1992
ACM
15 years 6 months ago
1992
ACM
This paper evaluates the performance of the parallel, main-memory DBMS, PRISMA/DB. First, an architecture for parallel query execution is presented. A performance model for the ex...
100
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MICRO
2009
IEEE
15 years 9 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
109
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ESTIMEDIA
2004
Springer
15 years 8 months ago
2004
Springer
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...