955 search results - page 45 / 191 » Performance optimization of multiple memory architectures fo... |
ISCA
2006
IEEE
13 years 9 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
IISWC
2009
IEEE
14 years 3 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
SIGGRAPH
1994
ACM
14 years 1 months ago
1994
ACM
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...