Sciweavers

955 search results - page 47 / 191
» Performance optimization of multiple memory architectures fo...
Sort
View
DATE
2000
IEEE
101views Hardware» more  DATE 2000»
14 years 1 months ago
Memory Arbitration and Cache Management in Stream-Based Systems
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
Françoise Harmsze, Adwin H. Timmer, Jef L. ...
ANCS
2009
ACM
13 years 7 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
VLDB
1999
ACM
145views Database» more  VLDB 1999»
14 years 1 months ago
DBMSs on a Modern Processor: Where Does Time Go?
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill...
HPCA
2002
IEEE
14 years 9 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
IPPS
2010
IEEE
13 years 7 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...