955 search results - page 49 / 191 » Performance optimization of multiple memory architectures fo... |
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
There is a strong need now for compilers of embedded systems to find effective ways of optimizing series of loop-nests, wherein majority of the memory references occur in the fo...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
ASPLOS
1992
ACM
14 years 1 months ago
1992
ACM
Next generation computer systems will have gigabytes of physical memory and processors in the 200 MIPS range or higher. While this trend suggests that memory management for most p...
CASES
2001
ACM
14 years 22 days ago
2001
ACM
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
ISCA
2006
IEEE
13 years 9 months ago
2006
IEEE
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...