49 search results - page 4 / 10 » Performance prediction for a code with data-dependent runtim... |
CODES
2005
IEEE
14 years 3 months ago
2005
IEEE
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
RTAS
2010
IEEE
13 years 8 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
AINA
2009
IEEE
14 years 4 months ago
2009
IEEE
The architectures which support modern supercomputing machinery are as diverse today, as at any point during the last twenty years. The variety of processor core arrangements, thr...
MICRO
1998
IEEE
14 years 2 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
CODES
2004
IEEE
14 years 1 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...