23 search results - page 4 / 5 » Performance-Driven Interconnect Design Based on Distributed ... |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
ISPD
2003
ACM
14 years 5 days ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
IPPS
2005
IEEE
14 years 15 days ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...