Sciweavers

70 search results - page 7 / 14
» Performance-Driven Interconnect Global Routing
Sort
View
ISVLSI
2007
IEEE
150views VLSI» more  ISVLSI 2007»
14 years 3 months ago
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Pa...
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
14 years 4 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
SPAA
2004
ACM
14 years 3 months ago
Adaptive channel queue routing on k-ary n-cubes
This paper introduces a new adaptive method, Channel Queue Routing (CQR), for load-balanced routing on k-ary n-cube interconnection networks. CQR estimates global congestion in th...
Arjun Singh, William J. Dally, Amit K. Gupta, Bria...
ISPD
1999
ACM
106views Hardware» more  ISPD 1999»
14 years 1 months ago
Timing driven maze routing
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Sung-Woo Hur, Ashok Jagannathan, John Lillis
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden