Sciweavers

436 search results - page 56 / 88
» Performance-Driven Processor Allocation
Sort
View
CODES
2002
IEEE
14 years 1 months ago
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to...
Mohamed Shalan, Vincent John Mooney III
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 9 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
ICCD
2006
IEEE
183views Hardware» more  ICCD 2006»
14 years 5 months ago
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs. In this paper, ...
Sanjay Pant, David Blaauw
ECRTS
2007
IEEE
14 years 3 months ago
On Controllability and Feasibility of Utilization Control in Distributed Real-Time Systems
Feedback control techniques have recently been applied to a variety of real-time systems. However, a fundamental issue that was left out is guaranteeing system controllability and...
Xiaorui Wang, Yingming Chen, Chenyang Lu, Xenofon ...
IEEEPACT
2005
IEEE
14 years 2 months ago
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
Lian Li 0002, Lin Gao 0002, Jingling Xue