Sciweavers

436 search results - page 60 / 88
» Performance-Driven Processor Allocation
Sort
View
CODES
2005
IEEE
13 years 10 months ago
Automated data cache placement for embedded VLIW ASIPs
Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficie...
Paul Morgan, Richard Taylor, Japheth Hossell, Geor...
KBS
2008
110views more  KBS 2008»
13 years 8 months ago
Intensity-based image registration using multiple distributed agents
Image registration is the process of geometrically aligning images taken from different sensors, viewpoints or instances in time. It plays a key role in the detection of defects o...
Roger J. Tait, Gerald Schaefer, Adrian A. Hopgood
PROCEDIA
2010
148views more  PROCEDIA 2010»
13 years 3 months ago
SysCellC: a data-flow programming model on multi-GPU
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
Dominique Houzet, Sylvain Huet, Anis Rahman
SIGMETRICS
2011
ACM
161views Hardware» more  SIGMETRICS 2011»
12 years 11 months ago
Modeling program resource demand using inherent program characteristics
The workloads in modern Chip-multiprocessors (CMP) are becoming increasingly diversified, creating different resource demands on hardware substrate. It is necessary to allocate h...
Jian Chen, Lizy Kurian John, Dimitris Kaseridis
ICCD
2004
IEEE
104views Hardware» more  ICCD 2004»
14 years 5 months ago
Exploiting Quiescent States in Register Lifetime
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...
Rama Sangireddy, Arun K. Somani