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MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 8 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
DAC
2009
ACM
14 years 11 months ago
Way Stealing:cache-assisted automatic instruction set extensions
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
HAPTICS
2009
IEEE
14 years 5 months ago
Visual versus haptic progressive guidance for training in a virtual dynamic task
The objective of this work is to demonstrate that progressive haptic guidance can accelerate and improve motor task training outcomes over visual or practice-only methods in a tra...
Joel C. Huegel, Marcia Kilchenman O'Malley
EUROGP
2009
Springer
125views Optimization» more  EUROGP 2009»
14 years 4 months ago
The Role of Population Size in Rate of Evolution in Genetic Programming
Abstract. Population size is a critical parameter that affects the performance of an Evolutionary Computation model. A variable population size scheme is considered potentially be...
Ting Hu, Wolfgang Banzhaf
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
14 years 4 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll