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IPPS
2005
IEEE
14 years 4 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ISCAS
2005
IEEE
96views Hardware» more  ISCAS 2005»
14 years 4 months ago
Stereo video coding system with hybrid coding based on joint prediction scheme
— Stereo video systems require double bandwidth and more than twice computational complexity relative to monovideo systems. Thus, An efficient coding scheme is necessary for tra...
Li-Fu Ding, Shao-Yi Chien, Yu-Wen Huang, Yu-Lin Ch...
VISUALIZATION
2005
IEEE
14 years 4 months ago
The Magic Volume Lens: An Interactive Focus+Context Technique for Volume Rendering
The size and resolution of volume datasets in science and medicine are increasing at a rate much greater than the resolution of the screens used to view them. This limits the amou...
Lujin Wang, Ye Zhao, Klaus Mueller, Arie E. Kaufma...
SI3D
2005
ACM
14 years 4 months ago
Automatic impostor placement for guaranteed frame rates and low memory requirements
Impostors are image-based primitives commonly used to replace complex geometry in order to reduce the rendering time needed for displaying complex scenes. However, a big problem i...
Stefan Jeschke, Michael Wimmer, Heidrun Schumann, ...
RT
2004
Springer
14 years 4 months ago
CC Shadow Volumes
We present a technique that uses culling and clamping (CC) for accelerating the performance of stencil-based shadow volume computation. Our algorithm reduces the fill requirement...
Brandon Lloyd, Jeremy Wend, Naga K. Govindaraju, D...