24 search results - page 1 / 5 » Phantom-BTB: a virtualized branch target buffer design |
ASPLOS
2009
ACM
14 years 11 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
CDES
2006
14 years 8 days ago
2006
Recently, several loop buffer designs have been proposed to reduce instruction fetch energy due to size and location advantage of loop buffer. Nevertheless, on design complexity di...
RTCSA
2009
IEEE
14 years 5 months ago
2009
IEEE
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
SAC
2006
ACM
14 years 4 months ago
2006
ACM
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
ISCA
1995
IEEE
14 years 2 months ago
1995
IEEE
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...