2749 search results - page 153 / 550 » Physical Design of the |
164
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ICCAD
2000
IEEE
15 years 10 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
166
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ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
510
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DAC
2012
ACM
13 years 8 months ago
2012
ACM
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
182
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TCAD
2008
15 years 6 months ago
2008
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
153
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SAC
2010
ACM
15 years 6 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...