9 search results - page 2 / 2 » Physical Planning Of On-Chip Interconnect Architectures |
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
ASPDAC
2001
ACM
14 years 1 months ago
2001
ACM
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical ...
IJES
2008
13 years 9 months ago
2008
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...