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» Physical Synthesis for CPLD Architectures
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NOCS
2007
IEEE
14 years 1 months ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
CODES
2005
IEEE
14 years 1 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
DAC
2009
ACM
14 years 8 months ago
Matching-based minimum-cost spare cell selection for design changes
Metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited b...
Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, H...
EMSOFT
2004
Springer
14 years 1 months ago
Loose synchronization of event-triggered networks for distribution of synchronous programs
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
Jan Romberg, Andreas Bauer 0002
CASES
2003
ACM
14 years 28 days ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara