301 search results - page 11 / 61 » Physical design techniques for optimizing RTA-induced variat... |
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
FTEDA
2006
13 years 8 months ago
2006
As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing process...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Large-scale process variations can significantly limit the practical utility of microelectro-mechanical systems (MEMS) for RF (radio frequency) applications. In this paper we desc...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
SAC
2010
ACM
13 years 8 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...