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ICCAD
2009
IEEE

Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography

13 years 9 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a `bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation. In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standardcell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an ILP-based maximization of `alternate' mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algori...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
Added 18 Feb 2011
Updated 18 Feb 2011
Type Journal
Year 2009
Where ICCAD
Authors Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
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