Sciweavers

301 search results - page 47 / 61
» Physical design techniques for optimizing RTA-induced variat...
Sort
View
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
14 years 29 days ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 5 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 9 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
HPCA
2006
IEEE
14 years 7 months ago
Construction and use of linear regression models for processor performance analysis
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
JEA
2006
90views more  JEA 2006»
13 years 7 months ago
Heuristics for estimating contact area of supports in layered manufacturing
Layered Manufacturing is a technology that allows physical prototypes of three-dimensional models to be built directly from their digital representation, as a stack of two-dimensi...
Ivaylo Ilinkin, Ravi Janardan, Michiel H. M. Smid,...