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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
13 years 11 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 16 days ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
ASYNC
2002
IEEE
161views Hardware» more  ASYNC 2002»
14 years 12 days ago
High-Speed QDI Asynchronous Pipelines
This paper introduces two new high-speed quasi delay insensitive (QDI) asynchronous pipeline templates. These new high throughput templates support complex non-linear pipeline str...
Recep O. Ozdag, Peter A. Beerel
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 21 days ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
ICASSP
2011
IEEE
12 years 11 months ago
A fully automated 2-DE gel image analysis pipeline for high throughput proteomics
Image analysis is still considered as the bottleneck in 2D-gel based expression proteomics analysis for biomarkers discovery. We are presenting a new end-to-end image analysis pip...
Panagiotis Tsakanikas, Elias S. Manolakos