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» Pipeline Timing Analysis Using a Trace-Driven Simulator
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CODES
1999
IEEE
14 years 2 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
RTAS
2008
IEEE
14 years 4 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
PRDC
2008
IEEE
14 years 4 months ago
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...
Viswanathan Subramanian, Arun K. Somani
RTS
2006
129views more  RTS 2006»
13 years 9 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
CW
2006
IEEE
14 years 3 months ago
Error Minimising Pipeline for Hi-Fidelity, Scalable Geospatial Simulation
The geospatial category of simulations is used to show how origin centric techniques can solve a number of accuracy related problems common to 3D computer graphics applications. P...
Chris Thorne