Sciweavers

74 search results - page 3 / 15
» Pipeline Vectorization for Reconfigurable Systems
Sort
View
IPPS
2006
IEEE
14 years 1 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
ISCAS
1995
IEEE
109views Hardware» more  ISCAS 1995»
13 years 11 months ago
System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit
Kevin J. Nowka, Michael J. Flynn
DAC
2009
ACM
14 years 8 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
FCCM
1999
IEEE
122views VLSI» more  FCCM 1999»
13 years 12 months ago
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
Andrew A. Chien, Jay H. Byun