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FCCM
2004
IEEE
121views VLSI» more  FCCM 2004»
13 years 11 months ago
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
Alireza Hodjat, Ingrid Verbauwhede
FPL
2009
Springer
85views Hardware» more  FPL 2009»
14 years 16 days ago
Generating high-performance custom floating-point pipelines
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...
Florent de Dinechin, Cristian Klein, Bogdan Pasca
ARC
2009
Springer
241views Hardware» more  ARC 2009»
14 years 2 months ago
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. ...
Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro
FPGA
2009
ACM
482views FPGA» more  FPGA 2009»
14 years 16 days ago
A 17ps time-to-digital converter implemented in 65nm FPGA technology
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
Claudio Favi, Edoardo Charbon
CAMP
2000
IEEE
14 years 10 days ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada