5 search results - page 1 / 1 » Pipelining Tradeoffs of Massively Parallel SuperCISC Hardwar... |
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
BMCBI
2010
13 years 10 months ago
2010
Background: Massively parallel sequencing readouts of epigenomic assays are enabling integrative genome-wide analyses of genomic and epigenomic variation. Pash 3.0 performs sequen...
ARC
2008
Springer
14 years 26 days ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
ISVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
ICDE
2010
IEEE
14 years 10 months ago
2010
IEEE
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...