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» Pipelining in Multi-Query Optimization
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CSREAESA
2004
13 years 8 months ago
Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators
To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flat-t...
Venkiteswaran Anantharam, Maojiao He, Krishna Nata...
CGF
2010
105views more  CGF 2010»
13 years 7 months ago
Streaming-Enabled Parallel Dataflow Architecture for Multicore Systems
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...
CGF
2008
139views more  CGF 2008»
13 years 7 months ago
CHC++: Coherent Hierarchical Culling Revisited
We present a new algorithm for efficient occlusion culling using hardware occlusion queries. The algorithm significantly improves on previous techniques by making better use of te...
Oliver Mattausch, Jirí Bittner, Michael Wim...
TVLSI
2008
120views more  TVLSI 2008»
13 years 7 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CCR
2004
153views more  CCR 2004»
13 years 7 months ago
Tree bitmap: hardware/software IP lookups with incremental updates
IP address lookup is challenging for high performance routers because it requires a longest matching prefix at speeds of up to 10 Gbps (OC-192). Existing solutions have poor updat...
Will Eatherton, George Varghese, Zubin Dittia