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» Place and Route for Secure Standard Cell Design
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USS
2004
13 years 8 months ago
Tor: The Second-Generation Onion Router
We present Tor, a circuit-based low-latency anonymous communication service. This second-generation Onion Routing system addresses limitations in the original design by adding per...
Roger Dingledine, Nick Mathewson, Paul F. Syverson
VLSID
2005
IEEE
105views VLSI» more  VLSID 2005»
14 years 8 days ago
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
R. Manimegalai, E. Siva Soumya, V. Muralidharan, B...
AINA
2007
IEEE
14 years 1 months ago
Random Oracle Instantiation in Distributed Protocols Using Trusted Platform Modules
The random oracle model is an idealized theoretical model that has been successfully used for designing many cryptographic algorithms and protocols. Unfortunately, a series of res...
Vandana Gunupudi, Stephen R. Tate
ISPD
2005
ACM
185views Hardware» more  ISPD 2005»
14 years 8 days ago
Dragon2005: large-scale mixed-size placement tool
In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partition...
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
13 years 12 months ago
Design of FPGA interconnect for multilevel metalization
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
Raphael Rubin, André DeHon