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» Planning as an architectural control mechanism
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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 7 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
DBKDA
2010
IEEE
127views Database» more  DBKDA 2010»
13 years 6 months ago
Failure-Tolerant Transaction Routing at Large Scale
—Emerging Web2.0 applications such as virtual worlds or social networking websites strongly differ from usual OLTP applications. First, the transactions are encapsulated in an AP...
Idrissa Sarr, Hubert Naacke, Stéphane Gan&c...
HPCA
2008
IEEE
14 years 7 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
MOBISYS
2008
ACM
14 years 7 months ago
Micro power management of active 802.11 interfaces
Wireless interfaces are major power consumers on mobile systems. Considerable research has improved the energy efficiency of elongated idle periods or created more elongated idle ...
Jiayang Liu, Lin Zhong
MOBIHOC
2008
ACM
14 years 7 months ago
Complexity in wireless scheduling: impact and tradeoffs
It has been an important research topic since 1992 to maximize stability region in constrained queueing systems, which includes the study of scheduling over wireless ad hoc networ...
Yung Yi, Alexandre Proutiere, Mung Chiang