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GLOBECOM
2006
IEEE
14 years 4 months ago
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
Rongsen He, José G. Delgado-Frias
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 3 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
PERCOM
2006
ACM
14 years 10 months ago
An E-Learning Platform for Academy and Industry Networks
The European project COMSON (Coupled Multiscale Simulation and Optimization in Nanoelectronics) is a Marie Curie RTN project that involves five partners from academia and three fr...
Giuseppe Ali, Eleonora Bilotta, Lorella Gabriele, ...
PDP
2010
IEEE
14 years 5 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 5 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...