As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
The European project COMSON (Coupled Multiscale Simulation and Optimization in Nanoelectronics) is a Marie Curie RTN project that involves five partners from academia and three fr...
Giuseppe Ali, Eleonora Bilotta, Lorella Gabriele, ...
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...